2/1/2022

Moore Machine Sequence Detector

Moore Machine Sequence Detector

A sequence detector is a sequential circuit that outputs a 1 when a particular pattern of bits sequentially arrives at its data input. Example: Design a simple sequence detector for the sequence 011. Include three outputs that indicate how many bits have been received in the correct sequence. (For example, each output could be connected to an LED.) 1) Draw a State Diagram (Moore) and then assign binary State Identifiers. A 000 B 001 C 011 D 111 X=0 X=0 X=0 X=0 X=1 X=1 X=1 X=1. ' Introduction to finite-state machines #Moore versus Mealy machines #Synchronous Mealy machines #Example: A parity checker! Today ' Example: A sequence detector FSM ' Example: A vending machine FSM 2 FSM design! FSM-design procedure 1. State diagram and state-transition table 2. State minimization 3. State assignment (or state encoding) 4.

In this post, let’s look at some examples of sequence detectors (110 & 11011). A sequence detector is a sequential circuit that outputs a 1 when a particular pattern of bits sequentially arrives at its data input.

Moore Machine:

A finite state machine, whose output is a function of the present state only. Moore model requires more number of states for implementing the function.


Mealy Machine:

Sequence

A finite state machine, whose output is a function of the present state and the present input. It requires less number of states for implementing the function.

Sequence: 110

State diagram – Moore
Code (Verilog)

State diagram – Mealy
Code (Verilog)

Simulation Results
Moore machine:
Mealy machine:

Moore Machine Sequence Detector Model

Moore

101 Sequence Detector

Overlap and Non-Overlap:

Overlap: The final bits of one sequence can be the start of another sequence.
Non-Overlap: The detector resets itself to the start state when the sequence has been detected.

In this post, let’s look at some examples of sequence detectors (110 & 11011). A sequence detector is a sequential circuit that outputs a 1 when a particular pattern of bits sequentially arrives at its data input.

Moore Machine:

A finite state machine, whose output is a function of the present state only. Moore model requires more number of states for implementing the function.


Mealy Machine:

A finite state machine, whose output is a function of the present state and the present input. It requires less number of states for implementing the function.

Sequence: 110

State diagram – Moore
Code (Verilog)

State diagram – Mealy
Code (Verilog)

Simulation Results
Moore machine:
Mealy machine:

Overlap and Non-Overlap:

Overlap: The final bits of one sequence can be the start of another sequence.
Non-Overlap: The detector resets itself to the start state when the sequence has been detected.