2/1/2022

1010 Sequence Detector Moore State Diagram

Last time, I presented a Verilog code together with Testbench for Sequence Detector using FSM. The sequence being detected was '1011'.

The state diagram for a Moore machine or Moore diagram is a diagram that associates an output value with each state. Moore machine is an output producer. Relationship with Mealy machines. As Moore and Mealy machines are both types of finite-state machines, they are equally expressive: either type can be used to parse a regular language. Design an FSM for serial sequence detector with the pattern '0110' with non-overlapping. Use Mealy Machine. Answer: Four states. A (no 0 detected state), b (one 0 detected state), c (01 detected state), and d (011 detected state). The state transition or flow diagram for the non-overlapping case will be.

This VHDL project presents a full VHDL code for Moore FSM Sequence Detector. A VHDL Testbench is also provided for simulation. The sequence to be detected is '1001'.

  • Figure 3: State diagram for „1010‟ sequence detector using Mealy machine (with overlapping) The Verilog implementation of this FSM can be found in Verilog file in the download section. Moore based sequence detector The same „1010‟ sequence detector is designed also in Moore machine to show the differences.
  • The sequence detector (a) Moore representation state diagram (b) Timing diagrams (c) State table and flip-flop inputs tabulation (d) K-map plots for D A and D B (e) Circuit implementation The state table and the tabulation of the flip-flop inputs for the Moore circuit are shown in Figure 8.9(c) and the K-map plots for the D flip-flops are shown.
  • If you check the code you can see that in each state we go to the next state depending on the current value of inputs.So this is a mealy type state machine. The testbench code used for testing the design is given below.It sends a sequence of bits ' to the module.

Sequence Detector Examples

Diagram
The Moore FSM state diagram for the sequence detector is shown in the following figure.

VHDL code for Moore FSM Sequence Detector is designed based on Moore FSM's state diagram and block diagram:

VHDL Testbench for Sequence Detector using Moore FSM:

Simulation Waveform for Moore FSM Sequence Detector in VHDL:

Sequence
As shown in the simulation waveform of the VHDL Moore FSM sequence detector, the detector output only goes high when the sequence '1001' is detected.
Verilog code for Moore FSM Sequence Detector: here.
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Diagram

1010 Sequence Detector Moore State Diagram Example

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